DS1035 Datasheet, PDF (34/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Architecture
MachXO2 Family Data Sheet
There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes:
• TN1087, Minimizing System Interruption During Configuration Using TransFR Technology (Appendix B)
• TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
Figure 2-22. SPI Core Block Diagram
Configuration
Logic
EFB
SPI Function
Core
Logic/
Routing
EFB
WISHBONE
Interface
SPI
Registers
Control
Logic
MISO
MOSI
SCK
MCSN
SCSN
Table 2-16 describes the signals interfacing with the SPI cores.
Table 2-16. SPI Core Signal Description
Signal Name I/O
spi_csn[0]
O
spi_csn[1..7]
O
spi_scsn
I
spi_irq
O
spi_clk
I/O
spi_miso
I/O
spi_mosi
I/O
ufm_sn
I
cfg_stdby
O
cfg_wake
O
Master/Slave
Master
Master
Slave
Master/Slave
Master/Slave
Master/Slave
Master/Slave
Slave
Master/Slave
Master/Slave
Description
SPI master chip-select output
Additional SPI chip-select outputs (total up to eight slaves)
SPI slave chip-select input
Interrupt request
SPI clock. Output in master mode. Input in slave mode.
SPI data. Input in master mode. Output in slave mode.
SPI data. Output in master mode. Input in slave mode.
Configuration Slave Chip Select (active low), dedicated for selecting the
User Flash Memory (UFM).
Stand-by signal – To be connected only to the power module of the MachXO2
device. The signal is enabled only if the “Wakeup Enable” feature has been
set within the EFB GUI, SPI Tab.
Wake-up signal – To be connected only to the power module of the MachXO2
device. The signal is enabled only if the “Wakeup Enable” feature has been
set within the EFB GUI, SPI Tab.
Hardened Timer/Counter
MachXO2 devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bi-directional,
16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter sup-
ports the following functions:
2-30