DS1035 Datasheet, PDF (13/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Architecture
MachXO2 Family Data Sheet
Table 2-4 provides signal descriptions of the PLL block.
Table 2-4. PLL Signal Descriptions
Port Name
I/O
Description
CLKI
CLKFB
PHASESEL[1:0]
PHASEDIR
PHASESTEP
CLKOP
CLKOS
CLKOS2
CLKOS3
I
Input clock to PLL
I
Feedback clock
I
Select which output is affected by Dynamic Phase adjustment ports
I
Dynamic Phase adjustment direction
I
Dynamic Phase step – toggle shifts VCO phase adjust by one step.
O
Primary PLL output clock (with phase shift adjustment)
O
Secondary PLL output clock (with phase shift adjust)
O
Secondary PLL output clock2 (with phase shift adjust)
O
Secondary PLL output clock3 (with phase shift adjust)
LOCK
DPHSRC
STDBY
RST
RESETM
RESETC
RESETD
O
PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and feed-
back signals.
O
Dynamic Phase source – ports or WISHBONE is active
I
Standby signal to power down the PLL
I
PLL reset without resetting the M-divider. Active high reset.
I
PLL reset - includes resetting the M-divider. Active high reset.
I
Reset for CLKOS2 output divider only. Active high reset.
I
Reset for CLKOS3 output divider only. Active high reset.
ENCLKOP
ENCLKOS
ENCLKOS2
ENCLKOS3
PLLCLK
PLLRST
PLLSTB
PLLWE
PLLADDR [4:0]
I
Enable PLL output CLKOP
I
Enable PLL output CLKOS when port is active
I
Enable PLL output CLKOS2 when port is active
I
Enable PLL output CLKOS3 when port is active
I
PLL data bus clock input signal
I
PLL data bus reset. This resets only the data bus not any register values.
I
PLL data bus strobe signal
I
PLL data bus write enable signal
I
PLL data bus address
PLLDATI [7:0]
PLLDATO [7:0]
PLLACK
I
PLL data bus data input
O
PLL data bus data output
O
PLL data bus acknowledge signal
sysMEM Embedded Block RAM Memory
The MachXO2-640/U and larger devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a
9-Kbit RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes
including data buffering, PROM for the soft processor and FIFO.
sysMEM Memory Block
The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be
used in a variety of depths and widths as shown in Table 2-5.
2-9