DS1035 Datasheet, PDF (35/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Architecture
MachXO2 Family Data Sheet
• Supports the following modes of operation:
– Watchdog timer
– Clear timer on compare match
– Fast PWM
– Phase and Frequency Correct PWM
• Programmable clock input source
• Programmable input clock prescaler
• One static interrupt output to routing
• One wake-up interrupt to on-chip standby mode controller.
• Three independent interrupt sources: overflow, output compare match, and input capture
• Auto reload
• Time-stamping support on the input capture unit
• Waveform generation on the output
• Glitch-free PWM waveform generation with variable PWM period
• Internal WISHBONE bus access to the control and status registers
• Stand-alone mode with preloaded control registers and direct reset input
Figure 2-23. Timer/Counter Block Diagram
EFB
Timer/Counter
Core
Logic
Routing
EFB
WISHBONE
Interface
Timer/
Counter
Registers
Control
Logic
PWM
Table 2-17. Timer/Counter Signal Description
Port
tc_clki
tc_rstn
tc_ic
tc_int
tc_oc
I/O
Description
I
Timer/Counter input clock signal
I
Register tc_rstn_ena is preloaded by configuration to always keep this pin enabled
I
Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If
enabled, a rising edge of this signal will be detected and synchronized to capture tc_cnt value
into tc_icr for time-stamping.
O
Without WISHBONE – Can be used as overflow flag
With WISHBONE – Controlled by three IRQ registers
O
Timer counter output signal
For more details on these embedded functions, please refer to TN1205, Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices.
2-31