DS1035 Datasheet, PDF (7/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Architecture
MachXO2 Family Data Sheet
Slices
Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2-1
shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU
contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8.
The control logic performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-
select and wider RAM/ROM functions.
Table 2-1. Resources and Modes Available per Slice
Slice
Slice 0
Slice 1
Slice 2
Slice 3
PFU Block
Resources
Modes
2 LUT4s and 2 Registers
Logic, Ripple, RAM, ROM
2 LUT4s and 2 Registers
Logic, Ripple, RAM, ROM
2 LUT4s and 2 Registers
Logic, Ripple, RAM, ROM
2 LUT4s and 2 Registers
Logic, Ripple, ROM
Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for posi-
tive/negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the
carry-chain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the
adjacent PFU). Table 2-2 lists the signals associated with Slices 0-3.
Figure 2-4. Slice Diagram
FCO To Different Slice/PFU
FXB
FXA
A1
B1
C1
D1
M1
M0
From
Routing
A0
B0
C0
D0
CO
LUT4 &
Carry
F/SUM
CI
LUT5
Mux
CO
LUT4 &
Carry _F/SUM
CI
Slice
OFX1
F1
D
Flip-flop/
Latch
Q1
To
Routing
OFX0
F0
D
Q0
Flip-flop/
Latch
CE
CLK
LSR
Memory &
Control
Signals
FCI From
Different
Slice/PFU
For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:
• WCK is CLK
• WRE is from LSR
• DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2
• WAD [A:D] is a 4-bit address from slice 2 LUT input
2-3