DS1035 Datasheet, PDF (27/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Architecture
MachXO2 Family Data Sheet
and differential input termination. The PCI clamp is enabled after V_CC and V_CCIO are at valid operating levels
and the device has been configured.
3. Top sysIO Buffer Pairs
The sysIO buffer pairs in the top bank of the device consist of two single-ended output drivers and two single-
ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the top also have differ-
ential and referenced I/O buffers. Half of the sysIO buffer pairs on the top edge have true differential outputs.
The sysIO buffer pair comprising of the A and B PIOs in every PIC on the top edge have a differential output
driver. The referenced input buffer can also be configured as a differential input buffer.
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V_CC and V_CCIO0 have reached V_PORUP level defined
in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the
POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all
V_CCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that
are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-
down to GND (some pins such as PROGRAMN and the JTAG pins have weak pull-up to V_CCIO as the default func-
tionality). The I/O pins will maintain the blank configuration until V_CC and V_CCIO (for I/O banks containing configura-
tion I/Os) have reached V_PORUP levels at which time the I/Os will take on the user-configured settings only after a
proper download/configuration.
There are various ways a user can ensure that there are no spurious signals on critical outputs as the device pow-
ers up. These are discussed in more detail in TN1202, MachXO2 sysIO Usage Guide.
Supported Standards
The MachXO2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS, LVTTL, and PCI. The buffer supports the LVTTL, PCI, LVCMOS 1.2, 1.5, 1.8, 2.5,
and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive
strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS,
MLVDS and LVPECL output emulation is supported on all devices. The MachXO2-640U, MachXO2-1200/U and
higher devices support on-chip LVDS output buffers on approximately 50% of the I/Os on the top bank. Differential
receivers for LVDS, BLVDS, MLVDS and LVPECL are supported on all banks of MachXO2 devices. PCI support is
provided in the bottom bank of theMachXO2-640U, MachXO2-1200/U and higher density devices. Table 2-11 sum-
marizes the I/O characteristics of the MachXO2 PLDs.
Tables 2-11 and 2-12 show the I/O standards (together with their supply and reference voltages) supported by the
MachXO2 devices. For further information on utilizing the sysIO buffer to support a variety of standards please see
TN1202, MachXO2 sysIO Usage Guide.
Table 2-11. I/O Support Device by Device
Number of I/O Banks
Type of Input Buffers
MachXO2-256,
MachXO2-640
4
Single-ended (all I/O banks)
Differential Receivers (all I/O
banks)
MachXO2-640U,
MachXO2-1200
4
Single-ended (all I/O banks)
Differential Receivers (all I/O
banks)
Differential input termination
(bottom side)
MachXO2-1200U
MachXO2-2000/U,
MachXO2-4000,
MachXO2-7000
6
Single-ended (all I/O banks)
Differential Receivers (all I/O
banks)
Differential input termination
(bottom side)
2-23