DS1035 Datasheet, PDF (64/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

DC and Switching Characteristics
MachXO2 Family Data Sheet
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Parameter
Description
Device
Min. Max. Min. Max. Min. Max. Units
MachXO2-1200ZE 0.66 — 0.68 — 0.80 — ns
t_HPLL
Clock to Data Hold - PIO Input ^{MachXO2-2000ZE 0.68 — 0.70 — 0.83 —}
ns
Register
MachXO2-4000ZE 0.68 — 0.71 — 0.84 — ns
MachXO2-7000ZE 0.73 — 0.74 — 0.87 — ns
MachXO2-1200ZE 5.14 — 5.69 — 6.20 — ns
Clock to Data Setup - PIO
MachXO2-2000ZE 5.11 — 5.67 — 6.17 —
ns
t_{SU_DELPLL}
Input Register with Data Input
Delay
MachXO2-4000ZE
5.27 — 5.84 — 6.35 —
ns
MachXO2-7000ZE 5.15 — 5.71 — 6.23 — ns
MachXO2-1200ZE -1.36 — -1.36 — -1.36 — ns
t_{H_DELPLL}
Clock to Data Hold - PIO Input ^{MachXO2-2000ZE}
Register with Input Data Delay _{MachXO2-4000ZE}
-1.35 — -1.35 — -1.35 —
-1.43 — -1.43 — -1.43 —
ns
ns
MachXO2-7000ZE -1.41 — -1.41 — -1.41 — ns
Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned⁹
t_DVA
Input Data Valid After CLK
— 0.382 — 0.401 — 0.417 UI
t_DVE
f_DATA
Input Data Hold After CLK
DDRX1 Input Data Speed
All MachXO2
devices, all sides
0.670 — 0.684 — 0.693 —
UI
— 140 — 116 — 98 Mbps
f_DDRX1
DDRX1 SCLK Frequency
— 70 — 58 — 49 MHz
Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered⁹
t_SU
Input Data Setup Before CLK
1.319 — 1.412 — 1.462 — ns
t_HO
f_DATA
Input Data Hold After CLK
DDRX1 Input Data Speed
All MachXO2
devices, all sides
0.717 — 1.010 — 1.340 — ns
— 140 — 116 — 98 Mbps
f_DDRX1
DDRX1 SCLK Frequency
— 70 — 58 — 49 MHz
Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned⁹
t_DVA
Input Data Valid After CLK
— 0.361 — 0.346 — 0.334 UI
t_DVE
Input Data Hold After CLK
MachXO2-640U,
0.602 — 0.625 — 0.648 —
UI
f_DATA
DDRX2 Serial Input Data
Speed
MachXO2-1200/U
and larger devices,
— 280 — 234 — 194 Mbps
f_DDRX2
DDRX2 ECLK Frequency
bottom side only
— 140 — 117 — 97 MHz
f_SCLK
SCLK Frequency
— 70 — 59 — 49 MHz
Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered⁹
t_SU
Input Data Setup Before CLK
0.472 — 0.672 — 0.865 — ns
t_HO
Input Data Hold After CLK
MachXO2-640U,
0.363 — 0.501 — 0.743 — ns
f_DATA
DDRX2 Serial Input Data
Speed
MachXO2-1200/U
and larger devices,
— 280 — 234 — 194 Mbps
f_DDRX2
DDRX2 ECLK Frequency
bottom side only
— 140 — 117 — 97 MHz
f_SCLK
SCLK Frequency
— 70 — 59 — 49 MHz
Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input - GDDRX4_RX.ECLK.Aligned⁹
t_DVA
t_DVE
f_DATA
f_DDRX4
f_SCLK
Input Data Valid After ECLK
Input Data Hold After ECLK
DDRX4 Serial Input Data
Speed
DDRX4 ECLK Frequency
SCLK Frequency
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
— 0.307 — 0.316 — 0.326 UI
0.662 — 0.650 — 0.649 —
UI
— 420 — 352 — 292 Mbps
— 210 — 176 — 146 MHz
— 53 — 44 — 37 MHz
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