DS1035 Datasheet, PDF (47/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

DC and Switching Characteristics
MachXO2 Family Data Sheet
sysIO Single-Ended DC Electrical Characteristics^{1, 2}
Input/Output
Standard
V_IL
Min. (V)³ Max. (V)
V_IH
Min. (V) Max. (V)
V_OL Max.
(V)
V_OH Min. I_OL Max.⁴ I_OH Max.⁴
(V)
(mA)
(mA)
4
-4
8
-8
LVCMOS 3.3
LVTTL
-0.3
0.8
2.0
3.6
0.4
V_CCIO - 0.4
12
-12
16
-16
24
-24
0.2
V_CCIO - 0.2
0.1
-0.1
4
-4
8
-8
LVCMOS 2.5
-0.3
0.7
1.7
3.6
0.4
V_CCIO - 0.4
12
-12
16
-16
0.2
V_CCIO - 0.2
0.1
-0.1
4
-4
LVCMOS 1.8
-0.3
0.35V_CCIO 0.65V_CCIO
3.6
0.4
V_CCIO - 0.4
8
-8
12
-12
0.2
V_CCIO - 0.2
0.1
-0.1
4
-4
LVCMOS 1.5
-0.3
0.35V_CCIO 0.65V_CCIO
3.6
0.4
V_CCIO - 0.4
8
-8
0.2
V_CCIO - 0.2
0.1
-0.1
4
-2
LVCMOS 1.2
-0.3
0.35V_CCIO 0.65V_CCIO
3.6
0.4
V_CCIO - 0.4
8
-6
0.2
V_CCIO - 0.2
0.1
-0.1
PCI
-0.3
0.3V_CCIO 0.5V_CCIO
3.6
0.1V_CCIO 0.9V_CCIO
1.5
-0.5
SSTL25 Class I
-0.3
V_REF - 0.18 V_REF + 0.18
3.6
0.54
V_CCIO - 0.62
8
8
SSTL25 Class II
-0.3
V_REF - 0.18 V_REF +0.18
3.6
NA
NA
NA
NA
SSTL18 Class I
-0.3
V_REF - 0.125 V_REF +0.125
3.6
0.40
V_CCIO - 0.40
8
8
SSTL18 Class II
-0.3
V_REF - 0.125 V_REF +0.125
3.6
NA
NA
NA
NA
HSTL18 Class I
-0.3
V_REF - 0.1 V_REF +0.1
3.6
0.40
V_CCIO - 0.40
8
8
HSTL18 Class II
-0.3
V_REF - 0.1 V_REF +0.1
3.6
NA
NA
NA
NA
1. MachXO2 devices allow LVCMOS inputs to be placed in I/O banks where V_CCIO is different from what is specified in the applicable JEDEC
specification. This is referred to as a ratioed input buffer. In a majority of cases this operation follows or exceeds the applicable JEDEC spec-
ification. The cases where MachXO2 devices do not meet the relevant JEDEC specification are documented in the table below.
2. MachXO2 devices allow for LVCMOS referenced I/Os which follow applicable JEDEC specifications. For more details about mixed mode
operation please refer to please refer to TN1202, MachXO2 sysIO Usage Guide.
3. The dual function I²C pins SCL and SDA are limited to a V_IL min of -0.25V or to -0.3V with a duration of <10ns.
4. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
Input Standard
LVCMOS 33
LVCMOS 25
LVCMOS 18
V_CCIO (V)
1.5
1.5
1.5
V_IL Max. (V)
0.685
1.687
1.164
3-8