DS1035 Datasheet, PDF (25/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Figure 2-17. Output Gearbox
D6
D Q ^T6
D4
ODDRx2_C
D2
D0
T4
DQ
D Q ^T2
CDN
D Q ^T0
S6
DQ
CE
S7
0
1
GND ₀
1
S4
DQ
0
CE
S5 ¹
Q67
0
1
D Q ^S2
0
CE
S3 ¹
Q45 ₀
1
D Q ^S0
0
CE
S1 ¹
Q23 ₀
1
Architecture
MachXO2 Family Data Sheet
D Q ^Q67
Q45
DQ
Q23
DQ
QC
Q01
DQ
Q/QA
D1
T1
DQ
D Q ^S1
0
CE
S0 1
Q12 ₀
1
Q10
DQ
D3
ODDRx2_A
D5
T3
DQ
Q D ^T5
D Q ^S3
0
CE
1
S2
Q34 ₀
1
Q32
DQ
S5
DQ
CE
S4
0
1
Q56 ₀
1
Q54
DQ
D7
ODDRx2_C
SCLK
SEL /0
UPDATE
ECLK0/1
Q D ^T7
D Q ^S7
0
CE
S6 ¹
GND ₀
1
Q76
DQ
More information on the output gearbox is available in TN1203, Implementing High-Speed Interfaces with
MachXO2 Devices.
DDR Memory Support
Certain PICs on the right edge of MachXO2-640U, MachXO2-1200/U and larger devices, have additional circuitry
to allow the implementation of DDR memory interfaces. There are two groups of 14 or 12 PIOs each on the right
edge with additional circuitry to implement DDR memory interfaces. This capability allows the implementation of up
to 16-bit wide memory interfaces. One PIO from each group contains a control element, the DQS Read/Write
2-21