DS1035 Datasheet, PDF (70/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

DC and Switching Characteristics
MachXO2 Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter
Descriptions
Conditions
f_IN
Input Clock Frequency (CLKI, CLKFB)
f_OUT
Output Clock Frequency (CLKOP, CLKOS,
CLKOS2)
f_OUT2
Output Frequency (CLKOS3 cascaded from
CLKOS2)
f_VCO
PLL VCO Frequency
f_PFD
Phase Detector Input Frequency
AC Characteristics
t_DT
t_{DT_TRIM}⁷
t_PH⁴
Output Clock Duty Cycle
Edge Duty Trim Accuracy
Output Phase Accuracy
Output Clock Period Jitter
Output Clock Cycle-to-cycle Jitter
t_OPJIT^{1, 8}
Output Clock Phase Jitter
Output Clock Period Jitter (Fractional-N)
t_SPO
t_W
t_LOCK^{2, 5}
t_UNLOCK
Output Clock Cycle-to-cycle Jitter 
(Fractional-N)
Static Phase Offset
Output Clock Pulse Width
PLL Lock-in Time
PLL Unlock Time
t_IPJIT⁶
Input Clock Period Jitter
t_HI
t_LO
t_STABLE⁵
t_RST
t_RSTREC
t_{RST_DIV}
t_{RSTREC_DIV}
t_ROTATE-SETUP
Input Clock High Time
Input Clock Low Time
STANDBY High to PLL Stable
RST/RESETM Pulse Width
RST Recovery Time
RESETC/D Pulse Width
RESETC/D Recovery Time
PHASESTEP Setup Time
Without duty trim selected³
f_OUT > 100MHz
f_OUT < 100MHz
f_OUT > 100MHz
f_OUT < 100MHz
f_PFD > 100MHz
f_PFD < 100MHz
f_OUT > 100MHz
f_OUT < 100MHz
f_OUT > 100MHz
f_OUT < 100MHz
Divider ratio = integer
At 90% or 10%³
f_PFD  20 MHz
f_PFD < 20 MHz
90% to 90%
10% to 10%
Min.
7
Max.
400
1.5625 400
0.0122 400
200 800
7
400
45
-75
-6
—
—
—
—
—
—
—
—
—
—
-120
0.9
—
—
—
—
0.5
0.5
—
1
1
10
1
10
55
75
6
150
0.007
180
0.009
160
0.011
230
0.12
230
0.12
120
—
15
50
1,000
0.02
—
—
15
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
MHz
%
%
%
ps p-p
UIPP
ps p-p
UIPP
ps p-p
UIPP
ps p-p
UIPP
ps p-p
UIPP
ps
ns
ms
ns
ps p-p
UIPP
ns
ns
ms
ns
ns
ns
ns
ns
3-31