DS1035 Datasheet, PDF (103/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

MachXO2 Family Data Sheet
Supplemental Information
April 2012
Data Sheet DS1035
For Further Information
A variety of technical notes for the MachXO2 family are available on the Lattice web site.
• TN1198, Power Estimation and Management for MachXO2 Devices
• TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide
• TN1201, Memory Usage Guide for MachXO2 Devices
• TN1202, MachXO2 sysIO Usage Guide
• TN1203, Implementing High-Speed Interfaces with MachXO2 Devices
• TN1204, MachXO2 Programming and Configuration Usage Guide
• TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
• TN1206, MachXO2 SRAM CRC Error Detection Usage Guide
• TN1207, Using TraceID in MachXO2 Devices
• TN1074, PCB Layout Recommendations for BGA Packages
• TN1087, Minimizing System Interruption During Configuration Using TransFR Technology
• AN8086, Designing for Migration from MachXO2-1200-R1 to Standard (non-R1) Devices
• AN8066, Boundary Scan Testability with Lattice sysIO Capability
• MachXO2 Device Pinout Files
• Thermal Management document
• Lattice design tools
For further information on interface standards, refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, LVDS, DDR, DDR2, LPDDR): www.jedec.org
• PCI: www.pcisig.com
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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DS1035 Further Info_01.3