DS1035 Datasheet, PDF (61/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

DC and Switching Characteristics
MachXO2 Family Data Sheet
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Parameter
Description
Device
Min. Max. Min. Max. Min. Max. Units
LPDDR⁹
t_DVADQ
Input Data Valid After DQS
Input
— 0.369 — 0.395 — 0.421 UI
t_DVEDQ
Input Data Hold After DQS
Input
0.529 — 0.530 — 0.527 —
UI
t_DQVBS
t_DQVAS
Output Data Invalid Before
DQS Output
MachXO2-1200/U and ^{0.25 — 0.25 — 0.25 —}
UI
Output Data Invalid After DQS
Output
larger devices, right
side only.
0.25 — 0.25 — 0.25 —
UI
f_DATA
MEM LPDDR Serial Data
Speed
— 280 — 250 — 208 Mbps
f_SCLK
f_LPDDR
DDR⁹
SCLK Frequency
LPDDR Data Transfer Rate
— 140 — 125 — 104 MHz
0 280 0 250 0 208 Mbps
t_DVADQ
Input Data Valid After DQS
Input
— 0.350 — 0.387 — 0.414 UI
t_DVEDQ
Input Data Hold After DQS
Input
0.545 — 0.538 — 0.532 —
UI
t_DQVBS
t_DQVAS
Output Data Invalid Before
DQS Output
MachXO2-1200/U and 0.25 — 0.25 — 0.25 —
larger devices, right
UI
Output Data Invalid After DQS side only.
Output
0.25 — 0.25 — 0.25 —
UI
f_DATA
f_SCLK
f_{MEM_DDR}
DDR2⁹
MEM DDR Serial Data Speed
SCLK Frequency
MEM DDR Data Transfer Rate
— 300 — 250 — 208 Mbps
— 150 — 125 — 104 MHz
N/A 300 N/A 250 N/A 208 Mbps
t_DVADQ
Input Data Valid After DQS
Input
— 0.360 — 0.378 — 0.406 UI
t_DVEDQ
Input Data Hold After DQS
Input
0.555 — 0.549 — 0.542 —
UI
t_DQVBS
t_DQVAS
Output Data Invalid Before
DQS Output
MachXO2-1200/U and ^{0.25 — 0.25 — 0.25 —}
UI
Output Data Invalid After DQS
Output
larger devices, right
side only.
0.25 — 0.25 — 0.25 —
UI
f_DATA
f_SCLK
f_{MEM_DDR2}
MEM DDR Serial Data Speed
SCLK Frequency
MEM DDR2 Data Transfer
Rate
— 300 — 250 — 208 Mbps
— 150 — 125 — 104 MHz
N/A 300 N/A 250 N/A 208 Mbps
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14V. Other
operating conditions, including industrial, can be extracted from the Diamond software.
2. General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load.
3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).
4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.
5. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).
6. For Generic DDRX1 mode t_SU = t_HO = (t_DVE - t_DVA - 0.03ns)/2.
7. The t_{SU_DEL} and t_{H_DEL} values use the SCLK_ZERHOLD default step size. Each step is 105ps (-6), 113ps (-5), 120ps (-4).
8. This number for general purpose usage. Duty cycle tolerance is +/-10%.
9. Duty cycle is +/- 5% for system usage.
10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.
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