DS1035 Datasheet, PDF (58/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

DC and Switching Characteristics
MachXO2 Family Data Sheet
-6
-5
-4
Parameter
Description
Device
Min. Max. Min. Max. Min. Max. Units
MachXO2-1200HC-HE 0.41 — 0.48 — 0.55 — ns
t_HPLL
Clock to Data Hold - PIO Input ^{MachXO2-2000HC-HE 0.42 — 0.49 — 0.56 —}
ns
Register
MachXO2-4000HC-HE 0.43 — 0.50 — 0.58 — ns
MachXO2-7000HC-HE 0.46 — 0.54 — 0.62 — ns
MachXO2-1200HC-HE 2.88 — 3.19 — 3.72 — ns
Clock to Data Setup - PIO
MachXO2-2000HC-HE 2.87 — 3.18 — 3.70 —
ns
t_{SU_DELPLL}
Input Register with Data Input
Delay
MachXO2-4000HC-HE
2.96
—
3.28
—
3.81
—
ns
MachXO2-7000HC-HE 3.05 — 3.35 — 3.87 — ns
MachXO2-1200HC-HE -0.83 — -0.83 — -0.83 — ns
t_{H_DELPLL}
Clock to Data Hold - PIO Input ^{MachXO2-2000HC-HE -0.83}
Register with Input Data Delay _{MachXO2-4000HC-HE -0.87}
—
—
-0.83
-0.87
—
—
-0.83
-0.87
—
—
ns
ns
MachXO2-7000HC-HE -0.91 — -0.91 — -0.91 — ns
Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned⁹
t_DVA
Input Data Valid After CLK
— 0.317 — 0.344 — 0.368 UI
t_DVE
f_DATA
Input Data Hold After CLK
DDRX1 Input Data Speed
All MachXO2 devices, ^{0.742 — 0.702 — 0.668 —}
UI
all sides
— 300 — 250 — 208 Mbps
f_DDRX1
DDRX1 SCLK Frequency
— 150 — 125 — 104 MHz
Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered⁹
t_SU
Input Data Setup Before CLK
0.566 — 0.560 — 0.538 — ns
t_HO
f_DATA
Input Data Hold After CLK
DDRX1 Input Data Speed
All MachXO2 devices, ^{0.778 — 0.879 — 1.090 —}
ns
all sides
— 300 — 250 — 208 Mbps
f_DDRX1
DDRX1 SCLK Frequency
— 150 — 125 — 104 MHz
Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned⁹
t_DVA
Input Data Valid After CLK
— 0.316 — 0.342 — 0.364 UI
t_DVE
Input Data Hold After CLK
MachXO2-640U,
0.710 — 0.675 — 0.679 —
UI
f_DATA
DDRX2 Serial Input Data
Speed
MachXO2-1200/U and
larger devices,
—
664
—
554
—
462 Mbps
f_DDRX2
DDRX2 ECLK Frequency
bottom side only
— 332 — 277 — 231 MHz
f_SCLK
SCLK Frequency
— 166 — 139 — 116 MHz
Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered⁹
t_SU
t_HO
f_DATA
f_DDRX2
f_SCLK
Input Data Setup Before CLK
0.233 — 0.219 — 0.198 — ns
Input Data Hold After CLK
DDRX2 Serial Input Data
Speed
DDRX2 ECLK Frequency
MachXO2-640U,
0.287 — 0.287 — 0.344 — ns
MachXO2-1200/U and
larger devices,
—
664
—
554
—
462 Mbps
bottom side only
— 332 — 277 — 231 MHz
SCLK Frequency
— 166 — 139 — 116 MHz
3-19