DS1035 Datasheet, PDF (16/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Architecture
MachXO2 Family Data Sheet
The EBR memory supports three forms of write behavior for single or dual port operation:
1. Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through – A copy of the input data appears at the output of the same port. This mode is supported for
all data widths.
3. Read-Before-Write – When new data is being written, the old contents of the address appears at the output.
FIFO Configuration
The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out,
RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The
Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.
Table 2-7 shows the range of programming values for these flags.
Table 2-7. Programmable FIFO Flag Ranges
Flag Name
Full (FF)
Almost Full (AF)
Almost Empty (AE)
Empty (EF)
N = Address bit width.
Programming Range
1 to max (up to 2^N-1)
1 to Full-1
1 to Full-1
0
The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset
that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset
state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is
in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from
the FIFO.
Memory Core Reset
The memory core contains data output latches for ports A and B. These are simple latches that can be reset syn-
chronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with
port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and
associated resets for both ports are as shown in Figure 2-9.
Figure 2-9. Memory Core Reset
Memory Core
Q D ^SET
Port A[18:0]
Output Data
Latches
Q D ^SET
Port B[18:0]
RSTA
RSTB
GSRN
Programmable Disable
2-12