DS1035 Datasheet, PDF (3/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Introduction
MachXO2 Family Data Sheet
Table 1-1. MachXO2™ Family Selection Guide
LUTs
Distributed RAM (Kbits)
EBR SRAM (Kbits)
Number of EBR SRAM
Blocks (9 Kbits/block)
UFM (Kbits)
HC²
Device Options _HE³
ZE⁴
Number of PLLs
Hardened Functions:
I²C
SPI
Timer/Counter
Packages
25 WLCSP⁵
(2.5 x 2.5mm, 0.4mm)
32 QFN⁶
(5 x 5mm, 0.5mm)
64 ucBGA
(4 x 4mm, 0.4mm)
100 TQFP
(14 x 14mm)
132 csBGA
(8 x 8mm, 0.5mm)
144 TQFP
(20 x 20mm)
184 csBGA⁷
(8 x 8mm, 0.5mm)
256 caBGA
(14 x 14mm, 0.8mm)
256 ftBGA
(17 x 17mm, 1.0mm)
332 caBGA
(17 x 17mm, 0.8mm)
484 fpBGA
(23 x 23mm, 1.0mm)
XO2-256
256
2
0
0
0
0
2
1
1
21
44
55
55
XO2-640
640
5
18
2
24
XO2-640U¹
640
5
64
XO2-1200
1280
10
64
7
7
64
64
0
1
1
2
2
2
1
1
1
1
1
1
18
78
79
79
104
107
107
1. Ultra high I/O device.
2. High performance with regulator – V_CC = 2.5V, 3.3V
3. High performance without regulator – V_CC = 1.2V
4. Low power without regulator – V_CC = 1.2V
5. WLCSP package only available for ZE devices.
6. QFN package only available for HC and ZE devices.
7. 184 csBGA package only available for HE devices.
XO2-1200U¹
1280
10
74
XO2-2000
2112
16
74
8
8
80
80
1
1
2
2
1
1
1
1
I/Os
79
104
111
206
206
206
XO2-2000U¹
2112
16
92
XO2-4000
4320
34
92
10
10
96
96
2
2
2
2
1
1
1
1
104
114
150
206
206
274
278
278
XO2-7000
6864
54
240
26
256
2
2
1
1
114
206
206
278
334
Introduction
The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from
256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature
Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-
engineered source synchronous I/O support, advanced configuration support including dual-boot capability and
hardened versions of commonly used functions such as SPI controller, I²C controller and timer/counter. These fea-
tures allow these devices to be used in low cost, high volume consumer and system applications.
The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has sev-
eral features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs
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