DS1035 Datasheet, PDF (60/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

DC and Switching Characteristics
MachXO2 Family Data Sheet
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Parameter
Description
Device
Min. Max. Min. Max. Min. Max. Units
Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered⁹
t_DVB
Output Data Valid Before CLK
Output
0.535 — 0.670 — 0.830 — ns
t_DVA
f_DATA
f_DDRX2
Output Data Valid After CLK
Output
DDRX2 Serial Output Data
Speed
DDRX2 ECLK Frequency
(minimum limited by PLL)
MachXO2-640U,
0.535 — 0.670 — 0.830 — ns
MachXO2-1200/U and
larger devices, top side — 664 — 554 — 462 Mbps
only
— 332 — 277 — 231 MHz
f_SCLK
SCLK Frequency
— 166 — 139 — 116 MHz
Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned⁹
t_DIA
Output Data Invalid After CLK
Output
— 0.200 — 0.215 — 0.230 ns
t_DIB
f_DATA
Output Data Invalid Before
CLK Output
DDRX4 Serial Output Data
Speed
MachXO2-640U,
— 0.200 — 0.215 — 0.230 ns
MachXO2-1200/U and
larger devices, top side
only
—
756
—
630
—
524 Mbps
f_DDRX4
DDRX4 ECLK Frequency
— 378 — 315 — 262 MHz
f_SCLK
SCLK Frequency
— 95 — 79 — 66 MHz
Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered⁹
t_DVB
Output Data Valid Before CLK
Output
0.455 — 0.570 — 0.710 — ns
t_DVA
f_DATA
f_DDRX4
Output Data Valid After CLK
Output
DDRX4 Serial Output Data
Speed
DDRX4 ECLK Frequency
(minimum limited by PLL)
MachXO2-640U,
0.455 — 0.570 — 0.710 — ns
MachXO2-1200/U and
larger devices, top side — 756 — 630 — 524 Mbps
only
— 378 — 315 — 262 MHz
f_SCLK
SCLK Frequency
7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1⁹
— 95 — 79 — 66 MHz
t_DVB
Output Data Valid Before CLK
Output
— 0.160 — 0.180 — 0.200 ns
t_DVA
f_DATA
f_DDR71
f_CLKOUT
Output Data Valid After CLK
Output
MachXO2-640U,
— 0.160 — 0.180 — 0.200 ns
DDR71 Serial Output Data
Speed
MachXO2-1200/U and
larger devices, top side
—
756
—
630
—
524 Mbps
DDR71 ECLK Frequency
only.
— 378 — 315 — 262 MHz
7:1 Output Clock Frequency
(SCLK) (minimum limited by
PLL)
— 108 — 90 — 75 MHz
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