DS1035 Datasheet, PDF (59/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

DC and Switching Characteristics
MachXO2 Family Data Sheet
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Parameter
Description
Device
Min. Max. Min. Max. Min. Max. Units
Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Aligned⁹
t_DVA
Input Data Valid After ECLK
— 0.290 — 0.320 — 0.345 UI
t_DVE
Input Data Hold After ECLK _{MachXO2-640U,}
0.739 — 0.699 — 0.703 —
UI
f_DATA
DDRX4 Serial Input Data
Speed
MachXO2-1200/U and
larger devices,
—
756
—
630
—
524 Mbps
f_DDRX4
DDRX4 ECLK Frequency
bottom side only
— 378 — 315 — 262 MHz
f_SCLK
SCLK Frequency
— 95 — 79 — 66 MHz
Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered⁹
t_SU
Input Data Setup Before ECLK
0.233 — 0.219 — 0.198 — ns
t_HO
Input Data Hold After ECLK _{MachXO2-640U,}
0.287 — 0.287 — 0.344 — ns
f_DATA
DDRX4 Serial Input Data
Speed
MachXO2-1200/U and
larger devices,
—
756
—
630
—
524 Mbps
f_DDRX4
DDRX4 ECLK Frequency
bottom side only
— 378 — 315 — 262 MHz
f_SCLK
SCLK Frequency
— 95 — 79 — 66 MHz
7:1 LVDS Inputs (GDDR71_RX.ECLK.7:1)⁹
t_DVA
t_DVE
f_DATA
f_DDR71
f_CLKIN
Input Data Valid After ECLK
Input Data Hold After ECLK
DDR71 Serial Input Data
Speed
DDR71 ECLK Frequency
7:1 Input Clock Frequency
(SCLK) (minimum limited by
PLL)
MachXO2-640U,
MachXO2-1200/U and
larger devices, bottom
side only
—
0.739
—
—
0.290
—
756
378
—
0.699
—
—
0.320
—
630
315
—
0.703
—
—
0.345
—
524
262
UI
UI
Mbps
MHz
— 108 — 90 — 75 MHz
Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned⁹
t_DIA
Output Data Invalid After CLK
Output
— 0.520 — 0.550 — 0.580 ns
t_DIB
Output Data Invalid Before
CLK Output
All MachXO2 devices,
all sides
— 0.520 — 0.550 — 0.580 ns
f_DATA
DDRX1 Output Data Speed
— 300 — 250 — 208 Mbps
f_DDRX1
DDRX1 SCLK frequency
— 150 — 125 — 104 MHz
Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered⁹
t_DVB
Output Data Valid Before CLK
Output
1.210 — 1.510 — 1.870 — ns
t_DVA
f_DATA
f_DDRX1
Output Data Valid After CLK
Output
DDRX1 Output Data Speed
DDRX1 SCLK Frequency
(minimum limited by PLL)
All MachXO2 devices, ^{1.210 — 1.510 — 1.870 —}
ns
all sides
— 300 — 250 — 208 Mbps
— 150 — 125 — 104 MHz
Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned⁹
t_DIA
Output Data Invalid After CLK
Output
— 0.200 — 0.215 — 0.230 ns
t_DIB
f_DATA
Output Data Invalid Before
CLK Output
DDRX2 Serial Output Data
Speed
MachXO2-640U,
— 0.200 — 0.215 — 0.230 ns
MachXO2-1200/U and
larger devices, top side
only
—
664
—
554
—
462 Mbps
f_DDRX2
f_SCLK
DDRX2 ECLK frequency
SCLK Frequency
— 332 — 277 — 231 MHz
— 166 — 139 — 116 MHz
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