DS1035 Datasheet, PDF (33/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Architecture
MachXO2 Family Data Sheet
Figure 2-21. I²C Core Block Diagram
Configuration
Logic
Power
Control
Core
Logic/
Routing
EFB
EFB
WISHBONE
Interface
I²C Function
I²C
Registers
Control
Logic
SCL
SDA
Table 2-15 describes the signals interfacing with the I²C cores.
Table 2-15. I²C Core Signal Description
Signal Name
i2c_scl
i2c_sda
i2c_irqo
cfg_wake
cfg_stdby
I/O
Bi-directional
Bi-directional
Output
Output
Output
Description
Bi-directional clock line of the I²C core. The signal is an output if the I²C core is in master
mode. The signal is an input if the I²C core is in slave mode. MUST be routed directly to the
pre-assigned I/O of the chip. Refer to the Pinout Information section of this document for
detailed pad and pin locations of I²C ports in each MachXO2 device.
Bi-directional data line of the I²C core. The signal is an output when data is transmitted from
the I²C core. The signal is an input when data is received into the I²C core. MUST be routed
directly to the pre-assigned I/O of the chip. Refer to the Pinout Information section of this
document for detailed pad and pin locations of I²C ports in each MachXO2 device.
Interrupt request output signal of the I²C core. The intended usage of this signal is for it to be
connected to the WISHBONE master controller (i.e. a microcontroller or state machine) and
request an interrupt when a specific condition is met. These conditions are described with
the I²C register definitions.
Wake-up signal – To be connected only to the power module of the MachXO2 device. The
signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I²C
Tab.
Stand-by signal – To be connected only to the power module of the MachXO2 device. The
signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I²C
Tab.
Hardened SPI IP Core
Every MachXO2 device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core
is configured as a master it will be able to control other SPI enabled chips connected to the SPI bus. When the core
is configured as the slave, the device will be able to interface to an external SPI master. The SPI IP core on
MachXO2 devices supports the following functions:
• Configurable Master and Slave modes
• Full-Duplex data transfer
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• LSB First or MSB First Data Transfer
• Interface to custom logic through 8-bit WISHBONE interface
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