DS1035 Datasheet, PDF (15/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Figure 2-8. sysMEM Memory Primitives
Architecture
MachXO2 Family Data Sheet
AD[12:0]
DI[8:0]
CLK
CE
OCE
RST
WE
CS[2:0]
EBR
DO[8:0]
DIA[8:0]
ADA[12:0]
CLKA
CEA
RSTA
WEA
CSA[2:0]
OCEA
DOA[8:0]
EBR
DI[8:0]
ADB[12:0]
CLKB
CEB
RSTB
WEB
CSB[2:0]
OCEB
DOB[8:0]
ADW[8:0]
DI[17:0]
BE[1:0]
CLKW
CEW
RST
CSW[2:0]
EBR
ADR[12:0]
CLKR
CER
DO[17:0]
OCER
CSR[2:0]
Single-Port RAM
True Dual Port RAM
Pseudo Dual Port RAM
DI[17:0]
CLKW
WE
RST
FULLI
CSW[1:0]
EBR
AFF
FF
AEF
EF
DO[17:0]
ORE
CLKR
RE
EMPTYI
CSR[1:0]
RPRST
AD[12:0]
CLK
CE
OCE
RST
CS[2:0]
EBR
DO[17:0]
FIFO RAM
ROM
Table 2-6. EBR Signal Descriptions
Port Name
Description
Active State
CLK
Clock
Rising Clock Edge
CE
Clock Enable
Active High
OCE¹
Output Clock Enable
Active High
RST
Reset
Active High
BE¹
Byte Enable
Active High
WE
Write Enable
Active High
AD
Address Bus
—
DI
Data In
—
DO
Data Out
—
CS
Chip Select
Active High
AFF
FIFO RAM Almost Full Flag
—
FF
FIFO RAM Full Flag
—
AEF
FIFO RAM Almost Empty Flag
—
EF
FIFO RAM Empty Flag
—
RPRST
FIFO RAM Read Pointer Reset
—
1. Optional signals.
2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively.
3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respec-
tively.
4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2).
5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the
read port chip select, ORE is the output read enable.
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