DS1035 Datasheet, PDF (5/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

MachXO2 Family Data Sheet
Architecture
January 2013
Data Sheet DS1035
Architecture Overview
The MachXO2 family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The
larger logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM
(EBRs). Figures 2-1 and 2-2 show the block diagrams of the various family members.
Figure 2-1. Top View of the MachXO2-1200 Device
Embedded Function
Block (EFB)
User Flash Memory
(UFM)
sysCLOCK PLL
On-chip Configuration
Flash Memory
PIOs Arranged into
sysIO Banks
sysMEM Embedded
Block RAM (EBR)
Programmable Function Units
with Distributed RAM (PFUs)
Note: MachXO2-256, and MachXO2-640/U are similar to MachXO2-1200. MachXO2-256 has a lower LUT count and no PLL or EBR blocks.
MachXO2-640 has no PLL, a lower LUT count and two EBR blocks. MachXO2-640U has a lower LUT count, one PLL and seven EBR blocks.
Figure 2-2. Top View of the MachXO2-4000 Device
sysCLOCK PLL
Embedded
Function Block(EFB)
User Flash
Memory (UFM)
On-chip Configuration
Flash Memory
PIOs Arranged into
sysIO Banks
sysMEM Embedded
Block RAM (EBR)
Programmable Function Units
with Distributed RAM (PFUs)
Note: MachXO2-1200U, MachXO2-2000/U and MachXO2-7000 are similar to MachXO2-4000. MachXO2-1200U and MachXO2-2000 have a lower LUT count,
one PLL, and eight EBR blocks. MachXO2-2000U has a lower LUT count, two PLLs, and 10 EBR blocks. MachXO2-7000 has a higher LUT count, two PLLs,
and 26 EBR blocks.
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DS1035 Architecture_01.5