DS1035 Datasheet, PDF (65/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

DC and Switching Characteristics
MachXO2 Family Data Sheet
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Parameter
Description
Device
Min. Max. Min. Max. Min. Max. Units
Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered⁹
t_SU
Input Data Setup Before ECLK
t_HO
Input Data Hold After ECLK _{MachXO2-640U,}
f_DATA
DDRX4 Serial Input Data
Speed
MachXO2-1200/U
and larger devices,
f_DDRX4
DDRX4 ECLK Frequency
bottom side only
f_SCLK
SCLK Frequency
7:1 LVDS Inputs – GDDR71_RX.ECLK.7.1⁹
0.434 — 0.535 — 0.630 — ns
0.385 — 0.395 — 0.463 — ns
— 420 — 352 — 292 Mbps
— 210 — 176 — 146 MHz
— 53 — 44 — 37 MHz
t_DVA
t_DVE
f_DATA
f_DDR71
f_CLKIN
Input Data Valid After ECLK
Input Data Hold After ECLK
DDR71 Serial Input Data
Speed
DDR71 ECLK Frequency
7:1 Input Clock Frequency
(SCLK) (minimum limited by
PLL)
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
— 0.307 — 0.316 — 0.326 UI
0.662 — 0.650 — 0.649 —
UI
— 420 — 352 — 292 Mbps
— 210 — 176 — 146 MHz
— 60 — 50 — 42 MHz
Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned⁹
t_DIA
Output Data Invalid After CLK
Output
— 0.850 — 0.910 — 0.970 ns
t_DIB
Output Data Invalid Before
CLK Output
All MachXO2
devices, all sides
— 0.850 — 0.910 — 0.970 ns
f_DATA
DDRX1 Output Data Speed
— 140 — 116 — 98 Mbps
f_DDRX1
DDRX1 SCLK frequency
— 70 — 58 — 49 MHz
Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered⁹
t_DVB
Output Data Valid Before CLK
Output
2.720 — 3.380 — 4.140 — ns
t_DVA
f_DATA
f_DDRX1
Output Data Valid After CLK
Output
DDRX1 Output Data Speed
DDRX1 SCLK Frequency
(minimum limited by PLL)
All MachXO2
devices, all sides
2.720 — 3.380 — 4.140 — ns
— 140 — 116 — 98 Mbps
— 70 — 58 — 49 MHz
Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned⁹
t_DIA
Output Data Invalid After CLK
Output
— 0.270 — 0.300 — 0.330 ns
t_DIB
f_DATA
Output Data Invalid Before
CLK Output
DDRX2 Serial Output Data
Speed
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only
— 0.270 — 0.300 — 0.330 ns
— 280 — 234 — 194 Mbps
f_DDRX2
f_SCLK
DDRX2 ECLK frequency
SCLK Frequency
— 140 — 117 —
— 70 — 59 —
97 MHz
49 MHz
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