DS1035 Datasheet, PDF(23/106 Page) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

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DS1035 Datasheet, PDF (23/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

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Architecture

MachXO2 Family Data Sheet

These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by

the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment

based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the

data to the device core synchronized to the low-speed system clock. Figure 2-16 shows a block diagram of the

input gearbox.

Figure 2-16. Input Gearbox

Q21 D Q Q0_

Q10

D Q T0

Q43

Q Q21

Q32

Q65

Q43

Q54

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D Q T4

Q65

Q_6

D Q T6

Q_6

Q54

Q65

Q54

Q32

Q43

D Q S3

D T3

Q32

Q10

Q21

ECLK0/1

SEL0

UPDATE

2-19

SCLK

▷