DS1035 Datasheet, PDF (32/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

Figure 2-20. Embedded Function Block Interface
Configuration
Logic
Power
Control
Core
Logic/
Routing
Embedded Function Block (EFB)
EFB
WISHBONE
Interface
I²C (Primary)
I²C (Secondary)
SPI
Timer/Counter
Architecture
MachXO2 Family Data Sheet
I/Os for I²C
(Primary)
I/Os for I²C
(Secondary)
I/Os for SPI
PLL0
PLL1
UFM
Indicates connection
through core logic/routing.
Hardened I²C IP Core
Every MachXO2 device contains two I²C IP cores. These are the primary and secondary I²C IP cores. Either of the
two cores can be configured either as an I²C master or as an I²C slave. The only difference between the two IP
cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core.
When the IP core is configured as a master it will be able to control other devices on the I²C bus through the inter-
face. When the core is configured as the slave, the device will be able to provide I/O expansion to an I²C Master.
The I²C cores support the following functionality:
• Master and Slave operation
• 7-bit and 10-bit addressing
• Multi-master arbitration support
• Clock stretching
• Up to 400 KHz data transfer speed
• General call support
• Interface to custom logic through 8-bit WISHBONE interface
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