MC68HC11F1_13 Datasheet, PDF (95/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
RCKB — SCI Baud Rate Clock Check (Test)
SCR[2:0] — SCI Baud Rate Selects
Selects receiver and transmitter bit rate based on output from baud rate prescaler
stage. Refer to the SCI baud rate generator block diagram.
SCR[2:0]
000
001
010
011
100
101
110
111
Table 7-2 Baud Rate Selection
Divide
Prescaler
By
1
2
4
8
16
32
64
128
Highest Baud Rate
(Prescaler Output from Previous Table)
4800
19200
76800
312500
4800
19200
76800
312500
2400
9600
38400
156250
1200
4800
19200
78125
600
2400
9600
39063
300
1200
4800
19531
150
600
2400
9766
75
300
1200
4883
—
150
600
2441
The prescaler bits, SCP[2:0], determine the highest baud rate, and the SCR[2:0] bits
select an additional binary submultiple (≥1, ≥2, ≥4, through ≥128) of this highest baud
rate. The result of these two dividers in series is the 16X receiver baud rate clock. The
SCR[2:0] bits are not affected by reset and can be changed at any time, although they
should not be changed when any SCI transfer is in progress.
Figure 7-3 and Figure 7-4 illustrate the SCI baud rate timing chain. The prescaler se-
lect bits determine the highest baud rate. The rate select bits determine additional di-
vide by two stages to arrive at the receiver timing (RT) clock rate. The baud rate clock
is the result of dividing the RT clock by 16.
SERIAL COMMUNICATIONS INTERFACE
TECHNICAL DATA
For More Information On This Product,
7-9
Go to: www.freescale.com