MC68HC11F1_13 Datasheet, PDF (81/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
SECTION 6 PARALLEL INPUT/OUTPUT
The MC68HC11F1 MCU has up to 54 input/output lines, depending on the operating
mode. The data bus of this microcontroller is nonmultiplexed. I/O lines are organized
into seven parallel ports. Ports with bidirectional pins have an associated data direc-
tion control register. This register (DDRx) contains a data direction control bit for each
bidirectional port line. The following table is a summary of the configuration and fea-
tures of each port.
Port
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Table 6-1 I/O Port Configuration
Input Pins
—
—
—
—
8
—
—
Output Pins
—
8
—
—
—
8
—
Bidirectional Pins
8
—
8
6
—
—
8
Shared Functions
Timer
High-Order Address
Data Bus
SCI and SPI
A/D Converter
Low-Order Address
Chip Select Outputs
Port pin function is mode dependent. Do not confuse pin function with the electrical
state of the pin at reset. Port pins are either driven to a specified logic level or are con-
figured as high impedance inputs. I/O pins configured as high-impedance inputs have
port data that is indeterminate. The contents of the corresponding latches are depen-
dent upon the electrical state of the pins during reset. In port descriptions, an “I” indi-
cates this condition. Port pins that are driven to a known logic level during reset are
shown with a value of either one or zero. Some control bits are unaffected by reset.
Reset states for these bits are indicated with a “U”.
6.1 Port A
Port A has eight bidirectional I/O pins and shares functions with the timer system.
PORTA — Port A Data
$1000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
I
I
I
I
I
I
I
I
Alt. Pin
Func.:
PAI
OC2
OC3
OC4 IC4/OC5 IC1
IC2
IC3
And/or:
OC1
OC1
OC1
OC1
OC1
—
—
—
PARALLEL INPUT/OUTPUT
TECHNICAL DATA
For More Information On This Product,
6-1
Go to: www.freescale.com