MC68HC11F1_13 Datasheet, PDF (149/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
SS
(INPUT)
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS IS HELD HIGH ON MASTER
1
SEE
NOTE
SEE
NOTE
4
5
6
7
MSB IN
10 (ref)
MASTER MSB OUT
13
13
5
13
4
BIT 6 - - - -1
11
10
BIT 6 - - - -1
NOTE: This first clock edge is generated internally but is not seen at the SCK pin.
12
12
LSB IN
11 (ref)
MASTER LSB OUT
12
Figure A-10 SPI Master Timing (CPHA = 0)
SS
(INPUT)
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS IS HELD HIGH ON MASTER
1
5
4
5
4
10 (ref)
MSB IN
MASTER MSB OUT
13
13
12
BIT 6 - - - -1
11
10
BIT 6 - - - -1
NOTE: This last clock edge is generated internally but is not seen at the SCK pin.
12
13
6
7
LSB IN
11 (ref)
MASTER LSB OUT
12
SEE
NOTE
SEE
NOTE
Figure A-11 SPI Master Timing (CPHA = 1)
TECHNICAL DATA
ELECTRICAL CHARACTERISTICS
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A-15