MC68HC11F1_13 Datasheet, PDF (115/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
OC1M — Output Compare 1 Mask
Bit 7
6
5
4
3
2
1
OC1M7 OC1M6 OC1M5 OC1M4 OC1M3
—
—
RESET:
0
0
0
0
0
0
0
OC1M[7:3] — Output Compare Masks
0 = OC1 is disabled.
1 = OC1 is enabled to control the corresponding pin of port A
Bits [2:0] — Not implemented
Always read zero
$100C
Bit 0
—
0
9.3.4 Output Compare Data Register
Use this register with OC1 to specify the data that is to be stored on the affected pin
of port A after a successful OC1 compare. When a successful OC1 compare occurs,
a data bit in OC1D is stored in the corresponding bit of port A for each bit that is set in
OC1M.
OC1D — Output Compare 1 Data
$100D
Bit 7
6
5
4
3
2
OC1D7 OC1D6 OC1D5 OC1D4 OC1D3
—
RESET:
0
0
0
0
0
0
1
Bit 0
—
—
0
0
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.
Bits [2:0] — Not implemented
Always read zero
9.3.5 Timer Counter Register
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A
full counter read addresses the most significant byte (MSB) first. A read of this address
causes the least significant byte (LSB) to be latched into a buffer for the next CPU cy-
cle so that a double-byte read returns the full 16-bit state of the counter at the time of
the MSB read cycle.
TCNT — Timer Counter
$100E, $100F
$100E Bit 15
14
13
12
11
10
$100F Bit 7
6
5
4
3
2
9
Bit 8 TCNT (High)
1
Bit 0 TCNT (Low)
TCNT resets to $0000. In normal modes, TCNT is a read-only register.
9.3.6 Timer Control Register 1
The bits of this register specify the action taken as a result of a successful OCx com-
pare.
TIMING SYSTEM
TECHNICAL DATA
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