MC68HC11F1_13 Datasheet, PDF (82/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
DDRA — Data Direction Register for Port A
RESET:
Bit 7
DDA7
0
6
DDA6
0
5
DDA5
0
4
DDA4
0
3
DDA3
0
DDA[7:0] — Data Direction for Port A
0 = Input
1 = Output
2
DDA2
0
1
DDA1
0
Bit 0
DDA0
0
$1001
NOTE
To enable PA3 as fourth input capture, set the I4/O5 bit in the PACTL
register. Otherwise, PA3 is configured as a fifth output compare out
of reset, with bit I4/O5 being cleared. If the DDA3 bit is set (configur-
ing PA3 as an output), and IC4 is enabled, writes to PA3 cause edges
on the pin to result in input captures. Writing to TI4/O5 has no effect
when the TI4/O5 register is acting as IC4. PA7 drives the pulse ac-
cumulator input but also can be configured for general-purpose I/O,
or output compare. Note that even when PA7 is configured as an out-
put, the pin still drives the pulse accumulator input.
6.2 Port B
Reset state is mode dependent. In single-chip or bootstrap modes, port B pins are
general-purpose outputs. In expanded and test modes, port B pins are high-order ad-
dress outputs and PORTB is not in the memory map.
PORTB — Port B Data
Bit 7
PB7
S. Chip or
Boot:
PB7
RESET: 0
Expan. or
Test: ADDR15
6
PB6
PB6
0
ADDR14
5
PB5
PB5
0
ADDR13
4
PB4
PB4
0
ADDR12
3
PB3
PB3
0
ADDR11
2
PB2
PB2
0
ADDR10
1
PB1
PB1
0
ADDR9
Bit 0
PB0
PB0
0
ADDR8
$1004
6.3 Port C
Reset state is mode dependent. In single-chip and bootstrap modes, port C pins are
high-impedance inputs. It is customary to have an external pull-up resistor on lines that
are driven by open-drain devices. In expanded or test modes, port C pins are data bus
inputs/outputs and PORTC is not in the memory map. The R/W signal is used to con-
trol the direction of data transfers.
The CWOM control bit in the OPT2 register disables port C's P-channel output drivers.
Because the N-channel driver is not affected by CWOM, setting CWOM causes port
C to become an open-drain-type output port suitable for wired-OR operation. In wired-
OR mode, (PORTC bits are at logic level zero), pins are actively driven low by the N-
channel driver. When a port C bit is at logic level one, the associated pin is in a high-
PARALLEL INPUT/OUTPUT
MC68HC11F1
6-2
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TECHNICAL DATA
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