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MC68HC11F1_13 Datasheet, PDF (148/158 Pages) Freescale Semiconductor, Inc – Technical Data
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Freescale Semiconductor, Inc.
Table A-8 Serial Peripheral Interface Timing
VDD = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH
Num
Characteristic
Symbol 2.0 MHz
3.0 MHz
Min Max Min Max
Operating Frequency
Master
Slave
fop(m)
fop(s)
dc 1.0 dc 1.5
dc 2.0 dc 3.0
1 Cycle Time
Master
Slave
tcyc(m) 2.0 — 2.0 —
tcyc(s) 500 — 333 —
2 Enable Lead Time
Master
Slave
(Note 2) tlead(m) — — — —
tlead(s) 250 — 240 —
3 Enable Lag Time
Master
Slave
(Note 2) tlag(m) — — — —
tlag(s) 250 — 240 —
4 Clock (SCK) High Time
Master
Slave
tw(SCKH)m 340 — 227 —
tw(SCKH)s 190 — 127 —
5 Clock (SCK) Low Time
Master
Slave
tw(SCKL)m 340 — 227 —
tw(SCKL)s 190 — 127 —
6 Data Setup Time (Inputs)
Master
Slave
tsu(m) 100 — 100 —
tsu(s) 100 — 100 —
7 Data Hold Time (Inputs)
Master
Slave
th(m)
th(s)
100 — 100 —
100 — 100 —
8 Access Time (Time to Data Active from
High-Impedance State)
Slave
ta
0 120 0 120
9 Disable Time (Hold Time to High-Impedance State)
Slave
tdis
— 240 — 167
10 Data Valid (After Enable Edge)
(Note 3) tv(s)
— 240 — 167
11 Data Hold Time (Outputs) (After Enable Edge)
tho
0—0—
12 Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
trm
— 100 — 100
trs
— 2.0 — 2.0
13 Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tfm
— 100 — 100
tfs
— 2.0 — 2.0
NOTES:
1. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins.
4.0 MHz
Min Max
dc 2.0
dc 4.0
2.0 —
250 —
——
200 —
——
200 —
130 —
85 —
130 —
85 —
100 —
100 —
100 —
100 —
0 120
— 125
— 125
0—
— 100
— 2.0
— 100
— 2.0
Unit
MHz
MHz
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
A-14
ELECTRICAL CHARACTERISTICS
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MC68HC11F1
TECHNICAL DATA
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