MC68HC11F1_13 Datasheet, PDF (144/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
Table A-5 Peripheral Port Timing
V_DD = 5.0 Vdc ± 5%, V_SS = 0 Vdc, T_A = T_L to T_H
Characteristic
Symbol 2.0 MHz
3.0 MHz
4.0 MHz
Min Max Min Max Min Max
Frequency of Operation (E-Clock Frequency)
f_o
dc 2.0 dc 3.0 dc 4.0
E-Clock Period
t_cyc 500 — 333 — 250 —
Peripheral Data Setup Time
t_PDSU 100 — 100 — 100 —
(MCU Read of Ports A, C, D, E, G)
Peripheral Data Hold Time
t_PDH 50 — 50 — 50 —
(MCU Read of Ports A, C, D, E, G)
Delay Time, Peripheral Data Write
(MCU Write to Port A)
(MCU Write to Ports B, C, D, F, and G
t_PWD = 1/4 t_cyc + 100 ns)
t_PWD
— 200 — 200 — 200
— 225 — 183 — 162
NOTES:
1. Ports C, D, and G timing is valid for active drive (CWOM, DWOM, and GWOM bits cleared).
2. All timing is shown with respect to 20% V_DD and 70% V_DD, unless otherwise noted.
Unit
MHz
ns
ns
ns
ns
MCU READ OF PORT
E
PORTS A, C, D, F
PORTS B, E, G
t_PDSU
t_PDH
t_PDSU
t_PDH
Figure A-7 Port Read Timing Diagram
E
PORTS C, D, F
PORTS A, B, G
MCU WRITE TO PORT
PREVIOUS PORT DATA
t_PWD
PREVIOUS PORT DATA
NEW DATA VALID
t_PWD
NEW DATA VALID
Figure A-8 Port Write Timing Diagram
A-10
ELECTRICAL CHARACTERISTICS
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MC68HC11F1
TECHNICAL DATA