MC68HC11F1_13 Datasheet, PDF (45/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
Register
Address
$x024
$x035
$x038
$x039
$x03C
$x03D
Table 4-2 Write Access Limited Registers
Register
Name
Timer Interrupt Mask 2 (TMSK2)
Block Protect Register (BPROT)
System Configuration Options 2 (OPT2)
System Configuration Options (OPTION)
Highest Priority I-bit and Miscellaneous (HPRIO)
RAM and I/O Map Register (INIT)
Must be Written in
First 64 Cycles
Note 1
Note 2
No
Note 3
No
Yes
Write One Time
Only
—
—
Note 4
—
Note 5
Note 6
Notes:
1. Bits 1 and 0 can be written once only in first 64 cycles. When SMOD = 1, these bits can be written any time. All
other bits can be written at any time.
2. Bits can be written to zero (protection disabled) once only in first 64 cycles or at any time in special modes. Bits
can be set to one at any time.
3. Bits 5, 4, 2, 1, and 0 can be written once only in first 64 cycles. When SMOD = 1, bits 5, 4, 2, 1, and 0 can be
written at any time. All other bits can be written at any time
4. Bit 5 (CLK4X) can be written only one time.
5. Bit 4 (IRV) can be written only one time.
6. Can be written once in first 64 cycles after reset in normal modes or at any time in special modes.
4.3.1 Mode Selection
The four mode variations are selected by the logic levels present on the MODA and
MODB pins at the rising edge of RESET. The MODA and MODB logic levels determine
the logic state of SMOD and MDA control bits in the HPRIO register.
After reset is released, the mode select pins no longer influence the MCU operating
mode. In single-chip operating mode, the MODA pin is connected to a logic level zero.
In expanded mode, MODA should be connected to V_DD through a pull-up resistor of
4.7 kΩ. The MODA pin also functions as the load instruction register (LIR) pin when
the MCU is not in reset. The open-drain active low LIR output pin drives low during the
first E cycle of each instruction (opcode fetch). The MODB pin also functions as stand-
by power input (V_STBY), which allows RAM contents to be maintained in absence of
V_DD. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for V_STBY voltage
requirements.
Refer to Table 4-3, which is a summary of mode pin operation, the mode control bits,
and the four operating modes.
Table 4-3 Hardware Mode Select Summary
Input Levels
at Reset
MODB
MODA
1
0
1
1
0
0
0
1
Mode
Single Chip
Expanded
Special Bootstrap
Special Test
Control Bits in HPRIO
(Latched at Reset)
RBOOT
SMOD
MDA
0
0
0
0
0
1
1
1
0
0
1
1
OPERATING MODES AND ON-CHIP MEMORY
TECHNICAL DATA
For More Information On This Product,
4-7
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