MC68HC11F1_13 Datasheet, PDF (122/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
E ÷ 64 CLOCK
(FROM MAIN TIMER)
PAOVI
PAOVF
PAII
PAIF
1
INTERRUPT
REQUESTS
2
PIN
PA7/
PAI/
OC1
FROM
MAIN TIMER
OC1
FROM DATA
DIRECTION
BIT FOR
PORT A PIN 7
TMSK2 INT ENABLES
INPUT BUFFER
AND
EDGE DETECTOR
OUTPUT
BUFFER
2:1
MUX
DATA BUS
TFLG2 INTERRUPT STATUS
PAI EDGE
PAEN
DISABLE
FLAG SETTING
CLOCK
OVERFLOW
PACNT 8-BIT COUNTER
ENABLE
PAEN
PACTL CONTROL
INTERNAL
DATA BUS
Figure 9-3 Pulse Accumulator
Crystal Frequency
(4∗E)
4.0 MHz
8.0 MHz
12.0 MHz
16.0 MHz
Table 9-5 Pulse Accumulator Timing
E Clock
(E)
1.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
Cycle Time
(1/E)
1000 ns
500 ns
333 ns
250 ns
2⁶/E
(64/E)
64 µs
32 µs
21.33 µs
16.0 µs
PACNT Overflow
(16384/E)
16.384 ms
8.192 ms
5.461 ms
4.096 ms
Pulse accumulator control bits are also located within two timer registers, TMSK2 and
TFLG2, as described in the following paragraphs.
9.6.1 Pulse Accumulator Control Register
Four of this register's bits control an 8-bit pulse accumulator system. Another bit en-
ables either the OC5 function or the IC4 function, while two other bits select the rate
for the real-time interrupt system.
9-16
TIMING SYSTEM
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MC68HC11F1
TECHNICAL DATA