MC68HC11F1_13 Datasheet, PDF (128/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
indicates when valid data is present in the result registers. The result registers are writ-
ten during a portion of the system clock cycle when reads do not occur, so there is no
conflict.
10.1.5 A/D Converter Clocks
The CSEL bit in the OPTION register selects whether the A/D converter uses the sys-
tem E clock or an internal RC oscillator for synchronization. When the A/D system is
operating with the MCU E clock, all switching and comparator functions are synchro-
nized to the MCU clocks. This allows the comparator results to be sampled at relatively
quiet clock times to minimize noise errors.
When E-clock frequency is below 750 kHz, charge leakage in the capacitor array can
cause errors, and the internal oscillator should be used. The RC clock is asynchronous
to the MCU internal E clock. Therefore, when the RC clock is used, additional errors
can occur because the comparator is sensitive to the additional system clock noise.
10.1.6 Conversion Sequence
A/D converter operations are performed in sequences of four conversions each. A
conversion sequence can repeat continuously or stop after one iteration. The conver-
sion complete flag (CCF) is set after the fourth conversion in a sequence to show the
availability of data in the result registers. Figure 10-3 shows the timing of a typical se-
quence. Synchronization is referenced to the system E clock.
E CLOCK
WRITE
TO
ADCTL
12 E CYCLES
SAMPLE ANALOG INPUT
MSB
4
CYCLES
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
22222222
CYC CYC CYC CYC CYC CYC CYC CYC
SUCCESSIVE APPROXIMATION SEQUENCE
END
REPEAT
SEQUENCE
IF
SCAN = 1
SET
CCF
FLAG
CONVERT FIRST
CONVERT SECOND
CONVERT THIRD
CONVERT FOURTH
CHANNEL
CHANNEL
CHANNEL
CHANNEL
AND UPDATE ADDR1
AND UPDATE ADDR2
AND UPDATE ADDR3
AND UPDATE ADDR4
0
32
64
96
128 E
CYCLES
Figure 10-3 A/D Conversion Sequence
10-4
ANALOG-TO-DIGITAL CONVERTER
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MC68HC11F1
TECHNICAL DATA