MC68HC11F1_13 Datasheet, PDF (120/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
9.4.2 Timer Interrupt Flag Register 2
Bits of this register indicate the occurrence of timer system events. Coupled with the
four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in
TMSK2 in the same position.
TFLG2 — Timer Interrupt Flag 2
Bit 7
6
5
4
3
2
1
TOF
RTIF PAOVF PAIF
—
—
—
RESET:
0
0
0
0
0
0
0
Clear flags by writing a one to the corresponding bit position(s).
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Bit 0
—
0
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to one at the end of every RTI period. To clear
RTIF, write a byte to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 9.6 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 9.6 Pulse Accumulator.
Bits [3:0] — Not implemented
Always read zero
9.4.3 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits con-
trol the pulse accumulator and IC4/OC5 functions.
PACTL — Pulse Accumulator Control
Bit 7
6
5
4
3
—
PAEN PAMOD PEDGE
—
RESET:
0
0
0
0
0
Bit 7 — Not implemented
Always reads zero
PAEN — Pulse Accumulator System Enable
Refer to 9.6 Pulse Accumulator.
PAMOD — Pulse Accumulator Mode
Refer to 9.6 Pulse Accumulator.
2
I4/O5
0
1
RTR1
0
Bit 0
RTR0
0
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9-14
TIMING SYSTEM
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MC68HC11F1
TECHNICAL DATA