MC68HC11F1_13 Datasheet, PDF (117/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
9.3.8 Timer Interrupt Flag Register 1
Bits in this register indicate when timer system events have occurred. Coupled with
the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a
polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in
the same position.
TFLG1 — Timer Interrupt Flag 1
$1023
RESET:
Bit 7
OC1F
0
6
OC2F
0
5
OC3F
0
4
OC4F
0
3
I4/O5F
0
2
IC1F
0
1
IC2F
0
Bit 0
IC3F
0
Clear flags by writing a one to the corresponding bit position(s).
OC1F–OC4F — Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
IC1F–IC3F — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
9.3.9 Timer Interrupt Mask Register 2
Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The
timer prescaler control bits are included in this register.
TMSK2 — Timer Interrupt Mask 2
Bit 7
6
5
4
3
TOI
RTII
PAOVI
PAII
—
RESET:
0
0
0
0
0
$1024
2
1
Bit 0
—
PR1
PR0
0
0
0
TOI — Timer Overflow Interrupt Enable
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to one
RTII — Real-Time Interrupt Enable
Refer to 9.4 Real-Time Interrupt.
PAOVI — Pulse Accumulator Overflow Interrupt Enable
Refer to 9.6.3 Pulse Accumulator Status and Interrupt Bits.
PAII — Pulse Accumulator Input Edge Interrupt Enable
Refer to 9.6.3 Pulse Accumulator Status and Interrupt Bits.
PR[1:0] — Timer Prescaler Select
These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0]
can only be written once, and the write must be within 64 cycles after reset. Refer to
Table 9-1 and Table 9-4 for specific timing values.
TECHNICAL DATA
TIMING SYSTEM
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