MC68HC11F1_13 Datasheet, PDF (19/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
2.5 Four Times E-Clock Frequency Output (4XOUT)
Although the circuit shown in Figure 2-6 will work for any M68HC11 MCU, the
MC68HC11F1 has an additional clock output that is four times the E-clock frequency.
This output (4XOUT) can be used to directly drive the EXTAL input of another
M68HC11 MCU. Refer to Figure 2-7. The 4XOUT output is enabled after reset and
can be disabled by clearing the CLK4X bit in the OPT2 register.
4XOUT
MC68HC11F1
EXTAL
XTAL
OSCILLATOR
CIRCUIT OR
CMOS-COMPATIBLE
CLOCK
NC OR
10 k – 100 k
LOAD
EXTAL
SECOND
XTAL
MCU
Figure 2-7 4XOUT Signal Driving a Second MCU
2.6 Interrupt Request (IRQ)
The IRQ input provides a means of generating asynchronous interrupt requests for the
CPU. Either falling-edge triggering or low-level triggering is selected by the IRQE bit
in the OPTION register. IRQ is always configured for level-sensitive triggering at reset.
Connect an external pull-up resistor, typically 4.7 kΩ, to V_DD when IRQ is used in a
level-sensitive wired-OR configuration. Refer to SECTION 5 RESETS AND INTER-
RUPTS.
2.7 Non-Maskable Interrupt (XIRQ)
The XIRQ input provides a means of requesting a non-maskable interrupt after reset
initialization. During reset, the X bit in the condition code register (CCR) is set and any
interrupt is masked until MCU software enables it. Because the XIRQ input is level
sensitive, it can be connected to a multiple-source wired-OR network with an external
pull-up resistor to V_DD. XIRQ is often used as a power loss detect interrupt.
Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ must be config-
ured for level-sensitive operation if there is more than one source of IRQ interrupt),
each source must drive the interrupt input with an open-drain type of driver to avoid
contention between outputs. There should be a single pull-up resistor near the MCU
interrupt input pin (typically 4.7 kΩ). There must also be an interlock mechanism at
each interrupt source so that the source holds the interrupt line low until the MCU rec-
ognizes and acknowledges the interrupt request. If one or more interrupt sources are
still pending after the MCU services a request, the interrupt line will still be held low
and the MCU will be interrupted again as soon as the interrupt mask bit in the condition
code register (CCR) is cleared (normally upon return from an interrupt). Refer to SEC-
TION 5 RESETS AND INTERRUPTS.
PIN DESCRIPTIONS
TECHNICAL DATA
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