MC68HC11F1_13 Datasheet, PDF (85/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
PORTF — Port F Data
S. Chip
or Boot:
RESET:
Expan.
or Test:
Bit 7
PF7
PF7
0
ADDR7
6
PF6
PF6
0
ADDR6
5
4
PF5
PF4
PF5
PF4
0
0
ADDR5 ADDR4
3
2
PF3
PF2
PF3
PF2
0
0
ADDR3 ADDR2
1
PF1
PF1
0
ADDR1
Bit 0
PF0
PF0
0
ADDR0
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6.7 Port G
Port G pins reset to high-impedance inputs except in expanded modes where reset
causes PG7 to become the CSPROG output. Alternate functions for port G bits [7:4]
are chip select outputs. All port G bits are bidirectional and have corresponding data
direction bits.
The GWOM control bit in the OPT2 register disables port G's P-channel output drivers.
Because the N-channel driver is not affected by GWOM, setting GWOM causes port
G to become an open-drain-type output port suitable for wired-OR operation. In wired-
OR mode, (PORTG bits are at logic level zero), pins are actively driven low by the N-
channel driver. When a port G bit is at logic level one, the associated pin is in a high-
impedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port G can be configured for wired-OR operation in any operating mode.
PORTG — Port G Data
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Bit 7
PG7
RESET:
I
Alt. Pin
Func.: CSPROG
6
PG6
I
CSGEN
5
PG5
I
CSIO1
4
PG4
I
CSIO2
3
PG3
I
—
2
PG2
I
—
1
PG1
I
—
Bit 0
PG0
I
—
DDRG — Data Direction Register for Port G
RESET:
Bit 7
DDG7
0
6
DDG6
0
5
DDG5
0
4
DDG4
0
3
DDG3
0
DDG[7:0] — Data Direction for Port G
0 = Input
1 = Output
2
DDG2
0
1
DDG1
0
Bit 0
DDG0
0
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6.8 System Configuration Options 2
The system configuration options 2 register controls several configuration parameters.
Bit 6, CWOM, is the only bit in this register that directly affects parallel I/O.
PARALLEL INPUT/OUTPUT
TECHNICAL DATA
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