MC68HC11F1_13 Datasheet, PDF (139/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
Table A-4 Control Timing
V_DD = 5.0 Vdc ± 5%, V_SS = 0 Vdc, T_A = T_L to T_H
Characteristic
Symbol 2.0 MHz
3.0 MHz
4.0 MHz Unit
Min Max Min Max Min Max
Frequency of Operation
f_o
dc 2.0 dc 3.0 dc 4.0 MHz
E-Clock Period
t_cyc
500 — 333 — 250 — ns
Crystal Frequency
f_XTAL — 8.0 — 12.0 — 16.0 MHz
External Oscillator Frequency
4 f_o
dc 8.0 dc 12.0 dc 16.0 MHz
Processor Control Setup Time
t_PCSU 175 — 133 — 113 — ns
t_PCSU = 1/4 t_cyc + 50 ns
Reset Input Pulse Width (Notes 2, 3)
PW_RSTL
(To Guarantee External Reset Vector)
16 — 16 — 16 — t_cyc
(Minimum Input Time;
1
—
1
—
1
— t_cyc
Can Be Preempted by Internal Reset)
Mode Programming Setup Time
t_MPS
2
—
2
—
2
— t_cyc
Mode Programming Hold Time
t_MPH
10 — 10 — 10 — ns
Interrupt Pulse Width, IRQ Edge-Sensitive Mode
PW_IRQ 520 — 353 — 270 — ns
PW_IRQ = t_cyc + 20 ns
Wait Recovery Startup Time
t_WRS
—
4
—
4
—
4
t_cyc
Timer Pulse Width, Input Capture Pulse Accumulator PW_TIM 520 — 353 — 270 — ns
Input
PW_TIM = t_cyc + 20 ns
NOTES:
1. All timing is shown with respect to 20% V_DD and 70% V_DD, unless otherwise noted.
2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four
clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt.
Refer to SECTION 5 RESETS AND INTERRUPTS for further detail.
3. PW_RSTL = 8 t_cyc minimum on mask set C94R only.
PA[3:0]1
PA[3:0]2
PA71,3
PA72,3
PWTIM
NOTES:
1. Rising edge sensitive input.
2. Falling edge sensitive input.
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
Figure A-2 Timer Inputs
ELECTRICAL CHARACTERISTICS
TECHNICAL DATA
For More Information On This Product,
A-5
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