MC68HC11F1_13 Datasheet, PDF (20/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
2.8 MODA and MODB (MODA/LIR and MODB/V_STBY)
During reset, MODA and MODB select one of the four operating modes. Refer to SEC-
TION 4 OPERATING MODES AND ON-CHIP MEMORY.
After the operating mode has been selected, the LIR pin provides an open-drain output
to indicate that execution of an instruction has begun. The LIR pin is configured for
wired-OR operation (only pulls low). A series of E-clock cycles occurs during execution
of each instruction. The LIR signal is asserted (drives low) during the first E-clock cycle
of each instruction (opcode fetch). This output is provided for assistance in program
debugging.
The V_STBY pin is used to input RAM standby power. The MCU is powered from the
V_DD signal unless the difference between the level of V_STBY and V_dd is greater than
one MOS threshold (about 0.7 volts). When these voltages differ by more than 0.7
volts, the internal 768-byte RAM and part of the reset logic are powered from V_STBY
rather than V_DD. This allows RAM contents to be retained without V_DD power applied
to the MCU. Reset must be driven low before V_DD is removed and must remain low
until V_DD has been restored to a valid level.
2.9 V_RH and V_RL
These pins provide the reference voltage for the analog-to-digital converter. Bypass
capacitors should be used to minimize noise on these signals. Any noise on V_RH and
V_RL will directly affect A/D accuracy.
2.10 R/W
In expanded and test modes, R/W indicates the direction of transfers on the external
data bus. A logic level one on this pin indicates that a read cycle is in progress. A logic
zero on this pin indicates that a write cycle is in progress and that no external device
should drive the data bus.
The E-clock can be used to enable external devices to drive data onto the data bus
during the second half of a read bus cycle (E clock high). R/W can then be used to
control the direction of data transfers. R/W drives low when data is being written to the
external data bus. R/W will remain low during consecutive data bus write cycles, such
as when a double-byte store occurs.
2.11 Port Signals
For the MC68HC11F1, 54 pins are arranged into six 8-bit ports: A, B, C, E, F, and G,
and one 6-bit port (D). Each of these seven ports serves a purpose other than I/O, de-
pending on the operating mode or peripheral functions selected. Note that ports B, C,
and F are available for I/O functions only in single-chip and bootstrap modes. The pins
of ports A, C, D, and G are fully bidirectional. Ports B and F are output-only ports. Port
E is an input-only port. Refer to Table 2-1 for details about the 54 port signals’ func-
tions within different operating modes.
PIN DESCRIPTIONS
MC68HC11F1
2-6
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