MC68HC11F1_13 Datasheet, PDF (44/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
$1028
$1029
$102A
$102B
$102C
$102D
$102E
$102F
$1030
$1031
$1032
$1033
$1034
$1035
$1036
$1037
$1038
$1039
$103A
$103B
$103C
$103D
$103E
$103F
$1040
to
$105B
$105C
$105D
$105E
$105F
Table 4-1 Register and Control Bit Assignments (Continued)
The register block can be remapped to any 4-Kbyte boundary.
Bit 7
SPIE
SPIF
Bit 7
TCLR
R8
TIE
TDRE
Bit 7
CCF
Bit 7
Bit 7
Bit 7
Bit 7
0
GWOM
ADPU
Bit 7
ODD
RBOOT
RAM3
TILOP
EE3`
6
SPE
WCOL
6
0
T8
TCIE
TC
6
0
6
6
6
6
0
CWOM
CSEL
6
EVEN
SMOD
RAM2
0
EE2
5
DWOM
0
5
SCP1
0
RIE
RDRF
5
SCAN
5
5
5
5
0
CLK4X
IRQE
5
0
MDA
RAM1
OCCR
EE1
4
MSTR
MODF
4
SCP0
M
ILIE
IDLE
4
MULT
4
4
4
4
PTCON
0
DLY
4
BYTE
IRV
RAM0
CBYP
EE0
3
CPOL
0
3
RCKB
WAKE
TE
OR
3
CD
3
3
3
3
BPRT3
0
CME
3
ROW
PSEL3
REG3
DISR
1
2
CPHA
0
2
SCR2
0
RE
NF
2
CC
2
2
2
2
BPRT2
0
FCME
2
ERASE
PSEL2
REG2
FCM
NOCOP
1
SPR1
0
1
SCR1
0
RWU
FE
1
CB
1
1
1
1
BPRT1
0
CR1
1
EELAT
PSEL1
REG1
FCOP
1
Bit 0
SPR0 SPCR
Bit 0 SPSR
Bit 0 SPDR
SCR0 BAUD
0 SCCR1
SBK SCCR2
0 SCSR
Bit 0 SCDR
CA ADCTL
Bit 0 ADR1
Bit 0 ADR2
Bit 0 ADR3
Bit 0 ADR4
BPRT0 BPROT
Reserved
Reserved
0 OPT2
CR0 OPTION
Bit 0 COPRST
EEPGM PPROG
PSEL0 HPRIO
REG0 INIT
0 TEST1
EEON CONFIG
Reserved
IO1SA
IO1EN
GA15
IO1AV
IO1SB
IO1PL
GA14
IO2AV
IO2SA
IO2EN
GA13
0
IO2SB
IO2PL
GA12
GNPOL
GSTHA
GCSPR
GA11
GAVLD
GSTHB
PCSEN
GA10
GSIZA
PSTHA
PSIZA
0
GSIZB
PSTHB
PSIZB
0
GSIZC
Reserved
CSSTRH
CSCTL
CSGADR
CSGSIZ
4.3 System Initialization
Registers and bits that control initialization and the basic operation of the MCU are pro-
tected against writes except under special circumstances. The following table lists reg-
isters that can be written only once after reset or that must be written within the first 64
cycles after reset.
OPERATING MODES AND ON-CHIP MEMORY
MC68HC11F1
4-6
For More Information On This Product,
TECHNICAL DATA
Go to: www.freescale.com