MC68HC11F1_13 Datasheet, PDF (61/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
CSIO1
Table 4-12 Chip Select Control Parameter Summary
Enable
Valid
Polarity
Size
Start Address
Stretch
IO1EN in CSCTL —
1 = On, off at reset (0)
IO1AV in CSGSIZ —
1 = Address valid, 0 = E valid
IO1PL in CSCTL —
1 = Active high, 0 = Active low
Fixed —
($x060–$x7FF)
$x060 —
“x” is determined by REG[3:0] in INIT
IO1SA–IO1SB in CSSTRH — 0, 1, 2, or 3 E clocks
CSIO2
Enable
Valid
Polarity
Size
Start Address
Stretch
IO2EN in CSCTL —
1 = On, off at reset (0)
IO2AV in CSGSIZ —
1 = Address valid, 0 = E valid
IO2PL in CSCTL —
1 = Active high, 0 = Active low
Fixed —
($x800–$xFFF)
$x800 —
“x” is determined by REG[3:0] in INIT
IO2SA–IO2SB in CSSTRH — 0, 1, 2, or 3 E clocks
CSPROG
Enable
Valid
Polarity
Size
Start Address
Stretch
Priority
PCSEN in CSCTL —
1 = On, on after reset in expanded modes
off after reset in single-chip modes
Fixed (Address valid)
Fixed (Active low)
PSIZA–PSIZB —
in CSCTL
0:0 = 64K ($0000–$FFFF)
0:1 = 32K ($8000–$FFFF)
1:0 = 16K ($C000–$FFFF)
1:1 = 8K ($E000–$FFFF)
Fixed (determined by size)
PSTHA–PSTHB in CSSTRH — 0, 1, 2, or 3 E clocks
1 cycle after reset in expanded mode
no delay after reset in all other modes
GCSPR in CSCTL —
1 = CSGEN above CSPROG
0 = CSPROG above CSGEN
CSGEN
Enable
Valid
Polarity
Size
Start Address
Stretch
Set size to 0K to disable — 1 = CSGEN above CSPROG
0 = CSPROG above CSGEN
GAVLD in CSGSIZ —
Address valid or E valid
GNPOL in CSGSIZ —
Active high or low
GSIZA–GSIZC in CSGSIZ — Refer to Table 4–12
GA[15:10] in CSGADR
GSTHA–GSTHB in CSSTRH — 0, 1, 2, or 3 E clocks
TECHNICAL DATA
OPERATING MODES AND ON-CHIP MEMORY
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