MC68HC11F1_13 Datasheet, PDF (57/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
$0000
$1000
$8000
$C000
x000 _{96-BYTE REGISTER}
x05F BLOCK
x060 _{I/O CHIP SELECT 1 REMAPPABLE TO}
x7FF (CSIO1)
4-KBYTE BOUNDARY
x800 _{I/O CHIP SELECT 2}
xFFF (CSIO2)
0000 PSIZ[A:B] = 0:0
64K
PROGRAM CHIP SELECT
(CSPROG)
PSIZ[A:B] = 0:1
8000 32K
$E000
$FE00
$FFFF
EXPANDED
MODE
PSIZ[A:B] = 1:0
C000 16K
PSIZ[A:B] = 1:1
E000 8K
FFFF
FFC0
VECTORS
FFFF
Figure 4-3 Address Map for I/O and Program Chip Selects
4.5.3 General-Purpose Chip Select
The general-purpose chip select (CSGEN) is the most flexible and has the most con-
trol bits. Polarity of the active state, E-valid or address-valid timing, size, starting ad-
dress, and clock delay are all programmable.
A single bit in CSCTL selects a priority between CSGEN and CSPROG. Bits in CSG-
SIZ select between address valid or E-clock valid timing, determine the polarity of the
active state and the address range of CSGEN. The value contained in the CSGADR
register determines the starting address for CSGEN. Depending on the size selected
for CSGEN, some bits in CSGADR will be invalid (don’t cares). Note that CSGEN is
disabled when a size of zero is selected. Refer to Figure 4-4.
TECHNICAL DATA
OPERATING MODES AND ON-CHIP MEMORY
For More Information On This Product,
Go to: www.freescale.com
4-19