MC68HC11F1_13 Datasheet, PDF (116/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
TCTL1 — Timer Control 1
$1020
Bit 7
6
5
4
3
2
1
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
RESET:
0
0
0
0
0
0
0
0
OM[2:5] — Output Mode
OL[2:5] — Output Level
These control bit pairs are encoded to specify the action taken after a successful OCx
compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to
Table 9-3 for the coding.
Table 9-2 Timer Output Compare Configuration
OMx
0
0
1
1
OLx
Action Taken on Successful Compare
0
Timer disconnected from output pin logic
1
Toggle OCx output line
0
Clear OCx output line to zero
1
Set OCx output line to one
9.3.7 Timer Interrupt Mask Register 1
Use this 8-bit register to enable or inhibit the timer input capture and output compare
interrupts.
TMSK1 — Timer Interrupt Mask 1
$1022
Bit 7
6
5
4
3
2
1
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
RESET:
0
0
0
0
0
0
0
0
OC1I–OC4I — Output Compare x Interrupt Enable
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt se-
quence is requested.
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When
I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit.
IC1I–IC3I — Input Capture x Interrupt Enable
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence
is requested.
NOTE
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in
TMSK1 enable the corresponding interrupt sources.
9-10
TIMING SYSTEM
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MC68HC11F1
TECHNICAL DATA