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MC68HC11F1_13 Datasheet, PDF (105/158 Pages) Freescale Semiconductor, Inc – Technical Data | |||
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Freescale Semiconductor, Inc.
8.5.2 Serial Peripheral Status
SPSR â Serial Peripheral Status Register
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Bit 7
6
5
4
3
2
1
Bit 0
SPIF WCOL
â
MODF
â
â
â
â
RESET:
0
0
0
0
0
0
0
0
SPIF â SPI Interrupt Complete Flag
SPIF is set upon completion of data transfer between the processor and the external
device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated.
To clear the SPIF bit, read the SPSR then access the SPDR. Unless SPSR is read
(with SPIF set) ï¬rst, attempts to write SPDR are inhibited.
WCOL â Write Collision
Clearing the WCOL bit is accomplished by reading the SPSR followed by an access of
SPDR. Refer to 8.3.4 Slave Select and 8.4 SPI System Errors.
0 = No write collision
1 = Write collision
Bit 5 â Not implemented
Always reads zero
MODF â Mode Fault
To clear the MODF bit, read the SPSR then write to the SPCR. Refer to 8.3.4 Slave
Select and 8.4 SPI System Errors.
0 = No mode fault
1 = Mode fault
Bits [3:0] â Not implemented
Always read zero
8.5.3 Serial Peripheral Data Register
The SPDR is used when transmitting or receiving data on the serial bus. Only a write
to this register initiates transmission or reception of a byte, and this only occurs in the
master device. At the completion of transferring a byte of data, the SPIF status bit is
set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss
of the byte that caused the overrun, the first SPIF must be cleared by the time a second
transfer of data from the shift register to the read buffer is initiated.
SPDR â SPI Data Register
Bit 7
6
5
4
3
2
Bit 7
6
5
4
3
2
SPI is double buffered in and single buffered out.
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1
Bit 0
1
Bit 0
SERIAL PERIPHERAL INTERFACE
TECHNICAL DATA
For More Information On This Product,
8-7
Go to: www.freescale.com
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