MC68HC11F1_13 Datasheet, PDF (123/158 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
PACTL — Pulse Accumulator Control
Bit 7
6
5
4
3
—
PAEN PAMOD PEDGE
—
RESET:
0
0
0
0
0
Bit 7 — Not implemented
Always reads zero
2
I4/O5
0
1
RTR1
0
Bit 0
RTR0
0
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PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
This bit has different meanings depending on the state of the PAMOD bit, as shown in
Table 9-6.
Table 9-6 Pulse Accumulator Edge Detection Control
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Action on Clock
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A zero on PAI inhibits counting.
A one on PAI inhibits counting.
Bit 3 — Not implemented
Always reads zero
I4/O5 — Input Capture 4/Output Compare 5
0 = Output compare 5 function enable (No IC4)
1 = Input capture 4 function enable (No OC5)
RTR[1:0] — RTI Interrupt Rate Selects
Refer to 9.4 Real-Time Interrupt.
9.6.2 Pulse Accumulator Count Register
This 8-bit read/write register contains the count of external input events at the PAI in-
put, or the accumulated count. The PACNT is readable even if PAI is not active in gat-
ed time accumulation mode. The counter is not affected by reset and can be read or
written at any time. Counting is synchronized to the internal PH2 clock so that incre-
menting and reading occur during opposite half cycles.
PACNT — Pulse Accumulator Count
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Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
TECHNICAL DATA
TIMING SYSTEM
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