MC908QY8CDWE Datasheet, PDF (92/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Low-Voltage Inhibit (LVI)
The LVI module contains a bandgap reference circuit and comparator. When the LVITRIP bit is cleared,
the default state at power-on reset, V_TRIPF is configured for the lower V_DD operating range. The actual
trip points are specified in 18.5 5-V DC Electrical Characteristics and 18.8 3-V DC Electrical
Characteristics.
Because the default LVI trip point after power-on reset is configured for low voltage operation, a system
requiring high voltage LVI operation must set the LVITRIP bit during system initialization. V_DD must be
above the LVI trip rising voltage, V_TRIPR, for the high voltage operating range or the MCU will immediately
go into LVI reset.
After an LVI reset occurs, the MCU remains in reset until V_DD rises above V_TRIPR. See Chapter 14 System
Integration Module (SIM) for the reset recovery sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
The LVI is enabled out of reset. The following bits located in the configuration register can alter the default
conditions.
• Setting the LVI power disable bit, LVIPWRD, disables the LVI.
• Setting the LVI reset disable bit, LVIRSTD, prevents the LVI module from generating a reset.
• Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
• Setting the LVI trip point bit, LVITRIP, configures the trip point voltage (V_TRIPF) for the higher V_DD
operating range.
10.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level, software can monitor V_DD by polling
the LVIOUT bit. In the configuration register, LVIPWRD must be cleared to enable the LVI module, and
LVIRSTD must be set to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls below the V_TRIPF level. In the configuration register, LVIPWRD
and LVIRSTD must be cleared to enable the LVI module and to enable LVI resets.
10.3.3 LVI Hysteresis
The LVI has hysteresis to maintain a stable operating condition. After the LVI has triggered (by having
V_DD fall below V_TRIPF), the MCU will remain in reset until V_DD rises above the rising trip point voltage,
V_TRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if V_DD is
approximately equal to V_TRIPF. V_TRIPR is greater than V_TRIPF by the typical hysteresis voltage, V_HYS.
10.3.4 LVI Trip Selection
LVITRIP in the configuration register selects the LVI protection range. The default setting out of reset is
for the low voltage range. Because LVITRIP is in a write-once configuration register, the protection range
cannot be changed after initialization.
NOTE
The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (V_TRIPF) may be lower than this. See the Electrical Characteristics
section for the actual trip point voltages.
MC68HC908QB8 Data Sheet, Rev. 3
90
Freescale Semiconductor