MC908QY8CDWE Datasheet, PDF (162/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Serial Peripheral Interface (SPI) Module
SPSCK CYCLE #
FOR REFERENCE
SPSCK; CPOL = 0
1
2
3
4
5
6
7
8
SPSCK; CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
SS; TO SLAVE
CAPTURE STROBE
Figure 15-4. Transmission Format (CPHA = 0)
Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may
be interpreted as a master or slave timing diagram because the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave.
The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS
line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select
input (SS) is low, so that only the selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as
general-purpose I/O not affecting the SPI. (See 15.3.6.2 Mode Fault Error.) When CPHA = 0, the first
SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first
SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave’s
SS pin must be toggled back to high and then low again between each byte transmitted as shown in
Figure 15-5.
MISO/MOSI
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
BYTE 1
BYTE 2
BYTE 3
Figure 15-5. CPHA/SS Timing
15.3.3.3 Transmission Format When CPHA = 1
Figure 15-6 shows an SPI transmission in which CPHA = 1. The figure should not be used as a
replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram because the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI)
pins are directly connected between the master and the slave. The MISO signal is the output from the
slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave.
The slave SPI drives its MISO output only when its slave select input (SS) is low, so that only the selected
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS
pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
15.3.6.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK
edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can
MC68HC908QB8 Data Sheet, Rev. 3
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Freescale Semiconductor