MC908QY8CDWE Datasheet, PDF (201/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Monitor Module (MON)
V_DD
N.C.
RST (PTA3)
1 μF
1 μF
DB9
2
3
MAX232
1 _C1+
+
3 _C1–
4 _C2+
+
5 _C2–
7
8
V_DD
N.C.
16
15
V+ ²
V– ⁶
+
1 μF
1 μF
+
10 kΩ*
V_DD
1 μF
+
10 kΩ
74HC125
10
6
5
74HC125
9
2
3
4
OSC1 (PTA5)
IRQ (PTA2)
PTA0
5
1
* Value not critical
V_DD
0.1 μF
PTA1
N.C.
PTA4
N.C.
V_SS
Figure 17-12. Monitor Mode Circuit (Internal Clock, No High Voltage)
The monitor code has been updated from previous versions of the monitor code to allow enabling the
internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out
of reset, is intended to support serial communication/programming at 9600 baud in monitor mode by using
the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if
programmed) to generate the desired internal frequency (3.2 MHz). Since this feature is enabled only
when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value
is not $FFFF) because entry into monitor mode in this case requires V_TST on IRQ. The IRQ pin must
remain low during this monitor session in order to maintain communication.
Table 17-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
• If $FFFE and $FFFF do not contain $FF (programmed state):
– The external clock is 9.8304 MHz
– IRQ = V_TST
• If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = V_DD (this can be implemented through the internal IRQ pullup)
• If $FFFE and $FFFF contain $FF (erased state):
– IRQ = V_SS (internal oscillator is selected, no external clock required)
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the
values on PTA1 and PTA4 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see 17.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor
199