MC908QY8CDWE Datasheet, PDF (109/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Port B
12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1
0
0
0
0
0
0
0
Figure 12-6. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 12-7 shows the
port B I/O logic.
READ DDRB
WRITE DDRB
WRITE PTB
RESET
DDRBx
PTBx
PTBPUEx
PULLUP
PTBx
READ PTB
Figure 12-7. Port B I/O Circuit
When DDRBx is a 1, reading PTB reads the PTBx data latch. When DDRBx is a 0, reading PTB reads
the logic level on the PTBx pin. The data latch can always be written, regardless of the state of its data
direction bit.
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor
107