MC908QY8CDWE Datasheet, PDF (150/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

System Integration Module (SIM)
14.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
14.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 14-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 14-3. Interrupt Sources
Priority
Source
Highest
Reset
SWI instruction
IRQ pin
Timer channel 0 interrupt
Timer channel 1 interrupt
Timer overflow interrupt
TIM channel 2 vector
TIM channel 3 vector
ESCI error vector
ESCI receive vector
ESCI transmit vector
SPI receive
Lowest
SPI transmit
Keyboard interrupt
ADC conversion complete interrupt
Flag
Mask⁽¹⁾
—
—
IRQF
CH0F
CH1F
TOF
CH2F
CH3F
OR, HF,
FE, PE
SCRF
SCTE, TC
SPRF,
OVRF,
MODF
SPTE
KEYF
COCO
—
—
IMASK
CH0IE
CH1IE
TOIE
CH2IE
CH3IE
ORIE, NEIE,
FEIE, PEIE
SCRIE
SCTIE, TCIE
SPRIE, ERRIE
SPTIE
IMASKK
AIEN
INT
Register
Flag
—
—
IF1
IF3
IF4
IF5
IF6
IF7
IF9
IF10
IF11
IF12
IF13
IF14
IF15
Vector
Address
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFF0–$FFF1
$FFEE–$FFEF
$FFEA–$FFEB
$FFE8–$FFE9
$FFE6–$FFE7
$FFE4–$FFE5
$FFE2–$FFE3
$FFE0–$FFE1
$FFDE–$FFDF
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
MC68HC908QB8 Data Sheet, Rev. 3
148
Freescale Semiconductor