MC908QY8CDWE Datasheet, PDF (185/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

I/O Signals
16.7 I/O Signals
The TIM module can share its pins with the general-purpose I/O pins. See Figure 16-1 for the port pins
that are shared.
16.7.1 TIM Channel I/O Pins (TCH3:TCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
TCH0 and TCH2 can be configured as buffered output compare or buffered PWM pins.
16.7.2 TIM Clock Pin (TCLK)
TCLK is an external clock input that can be the clock source for the counter instead of the prescaled
internal bus clock. Select the TCLK input by writing 1s to the three prescaler select bits, PS[2:0].
(See 16.8.1 TIM Status and Control Register.) The minimum TCLK pulse width is specified in 18.16 Timer
Interface Module Characteristics. The maximum TCLK frequency is the least of 4 MHz or bus
frequency ÷ 2.
16.8 Registers
The following registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 through TSC3)
• TIM channel registers (TCH0H:TCH0L through TCH3H:TCH3L)
16.8.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the counter
• Resets the counter
• Prescales the counter clock
Bit 7
6
5
4
3
Read: TOF
0
0
TOIE TSTOP
Write: 0
TRST
Reset: 0
0
1
0
0
= Unimplemented
2
1
Bit 0
PS2
PS1
PS0
0
0
0
Figure 16-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the counter reaches the modulo value programmed in the TIM counter
modulo registers. Clear TOF by reading the TSC register when TOF is set and then writing a 0 to TOF.
If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor
183